x86 or instruction
intel lock instruction
x86 atomic instructions
cmpxchg
x86 instruction set reference
x86 lock prefixamd64 instruction set
endbr64 instruction

DESCRIPTION: The XADD instruction adds the source to the destination and stores the sum in the destination, as with any addition. doesn't deal with instruction re-ordering by compiler) #define CACHELINE 64 __asm __volatile ( " lock; xaddl %0, %1 ; " : "+r" (v), "=m" (*p) : "m"What you want is XADDL %eax, (%edi) . Remember with gas syntax the destination is always the second value, and that you want to alter the "lock xaddl %0,%1" : "=r" (increment), "=m" (address) check out the 80x86 cmpxchg8b instruction (compare and exchange eight bytes). Cheers, Randy Hyde. This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. IA-32 Architecture Compatibility ¶. IA-32 processors earlier The DMB instruction is found in the ARM and Thumb2 instruction sets. + volatile int32_t *ptr) +{ + __asm__ __volatile__ ("lock; xaddl %0, In computer science, the fetch-and-add CPU instruction (FAA) atomically increments the contents of a memory location by a specified value.